1 cat28c17a 16k-bit cmos parallel eeprom features fast read access times: 200 ns low power cmos dissipation: ?active: 25 ma max. ?standby: 100 a max. simple write operation: ?on-chip address and data latches ?self-timed write cycle with auto-clear fast write cycle time: 10ms max end of write detection: ? data data data data data polling ?rdy/ bsy bsy bsy bsy bsy pin hardware write protection cmos and ttl compatible i/o 10,000 program/erase cycles 10 year data retention commercial,industrial and automotive temperature ranges description the cat28c17a is a fast, low power, 5v-only cmos parallel eeprom organized as 2k x 8-bits. it requires a simple interface for in-system programming. on-chip address and data latches, self-timed write cycle with auto-clear and v cc power up/down write protection eliminate additional timing and protection hardware. data polling and a rdy/ bsy pin signal the start and end of the self-timed write cycle. additionally, the cat28c17a features hardware write protection. the cat28c17a is manufactured using catalyst?s ad- vanced cmos floating gate technology. it is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. the device is available in jedec approved 28-pin dip and soic or 32-pin plcc pack- ages. block diagram addr. buffer & latches addr. buffer & latches inadvertent write protection control logic timer row decoder column decoder high voltage generator a 4 ? 10 ce oe we a 0 ? 3 i/o 0 ?/o 7 i/o buffers 2,048 x 8 eeprom array v cc da ta polling & rdy/busy rdy/busy ? 2004 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1075, rev. b h a l o g e n f r e e tm l e a d f r e e
cat28c17a 2 doc. no. 1075, rev. b pin configuration rdy/busy i/o 2 v ss i/o 5 13 14 22 21 20 17 9 12 25 24 23 rdy/busy i/o 1 oe a 10 ce a 3 a 2 a 1 a 0 5 6 7 8 1 2 3 4 a 7 a 6 a 5 a 4 a 9 28 27 26 v cc we a 8 a 6 a 5 a 4 a 3 5 6 7 8 a 2 a 1 a 0 nc 9 10 11 12 i/o 0 13 a 8 a 9 nc nc 29 28 27 26 oe a 10 ce 25 24 23 22 i/o 7 21 i/o 1 i/o 2 v ss nc i/o 3 i/o 4 i/o 5 14 15 16 17 18 19 20 4321323130 a 7 nc nc v cc we nc i/o 4 i/o 3 16 15 i/o 6 to p view i/o 6 19 18 11 i/o 0 i/o 7 nc 10 nc nc i/o 2 v ss i/o 5 13 14 22 21 20 17 9 12 25 24 23 rdy/busy i/o 1 oe a 10 ce a 3 a 2 a 1 a 0 5 6 7 8 1 2 3 4 a 7 a 6 a 5 a 4 a 9 28 27 26 v cc we a 8 i/o 4 i/o 3 16 15 i/o 6 19 18 11 i/o 0 i/o 7 nc 10 nc nc dip package (p, l) plcc package (n, g) soic package (j,w) (k, x) pin functions pin name function a 0 ?a 10 address inputs i/o 0 ?i/o 7 data inputs/outputs rdy/busy ready/busy status ce chip enable oe output enable we write enable v cc 5v supply v ss ground nc no connect mode selection mode ce we oe i/o power read l h l d out active byte write (we controlled) l h d in active byte write (ce controlled) l h d in active standby, and write inhibit h x x high-z standby read and write inhibit x h h high-z active capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test max. units conditions c i/o (1) input/output capacitance 10 pf v i/o = 0v c in (1) input capacitance 6 pf v in = 0v note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
cat28c17a 3 doc. no. 1075, rev. b *comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. absolute maximum ratings* temperature under bias ................. ?55 c to +125 c storage temperature ....................... ?65 c to +150 c voltage on any pin with respect to ground (2) ........... ?2.0v to +v cc + 2.0v v cc with respect to ground ............... ?2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (3) ........................ 100 ma d.c. operating characteristics v cc = 5v 10%, unless otherwise specified. limits symbol parameter min. typ. max. units test conditions i cc v cc current (operating, ttl) 35 ma ce = oe = v il , f = 1/t rc min, all i/o?s open i ccc (5) v cc current (operating, cmos) 25 ma ce = oe = v ilc , f = 1/t rc min, all i/o?s open i sb v cc current (standby, ttl) 1 ma ce = v ih , all i/o?s open i sbc (6) v cc current (standby, cmos) 100 a ce = v ihc , all i/o?s open i li input leakage current ?10 10 av in = gnd to v cc i lo output leakage current ?10 10 av out = gnd to v cc , ce = v ih v ih (6) high level input voltage 2 v cc +0.3 v v il (5) low level input voltage ?0.3 0.8 v v oh high level output voltage 2.4 v i oh = ?400 a v ol low level output voltage 0.4 v i ol = 2.1ma v wi write inhibit voltage 3.0 v reliability characteristics symbol parameter min. max. units test method n end (1) endurance 10,000 cycles/byte mil-std-883, test method 1033 t dr (1) data retention 10 years mil-std-883, test method 1008 v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(4) latch-up 100 ma jedec standard 17 note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) the minimum dc input voltage is ?0.5v. during transitions, inputs may undershoot to ?2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (3) output shorted for no more than one second. no more than one output shorted at a time. (4) latch-up protection is provided for stresses up to 100ma on address and data pins from ?1v to v cc +1v. (5) v ilc = ?0.3v to +0.3v. (6) v ihc = v cc ?0.3v to v cc +0.3v.
cat28c17a 4 doc. no. 1075, rev. b a.c. characteristics, read cycle v cc = 5v 10%, unless otherwise specified. 28c17a-20 symbol parameter min. max. units t rc read cycle time 200 ns t ce ce access time 200 ns t aa address access time 200 ns t oe oe access time 80 ns t lz (1) ce low to active output 0 ns t olz (1) oe low to active output 0 ns t hz (1)(2) ce high to high-z output 55 ns t ohz (1)(2) oe high to high-z output 55 ns t oh (1) output hold from address change 0 ns figure 1. a.c. testing input/output waveform(3) figure 2. a.c. testing load circuit (example) note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) output floating (high-z) is defined as the state when the external data line is no longer driven by the output buffer. (3) input rise and fall times (10% and 90%) < 10 ns. input pulse levels reference points 2.0 v 0.8 v 2.4 v 0.45 v 1.3v device under test 1n914 3.3k c l = 100 pf out c l includes jig capacitance
cat28c17a 5 doc. no. 1075, rev. b a.c. characteristics, write cycle v cc = 5v 10%, unless otherwise specified. 28c17a-20 symbol parameter min. max. units t wc write cycle time 10 ms t as address setup time 10 ns t ah address hold time 100 ns t cs ce setup time 0 ns t ch ce hold time 0 ns t cw (2) ce pulse time 150 ns t oes oe setup time 15 ns t oeh oe hold time 15 ns t wp (2) we pulse width 150 ns t ds data setup time 50 ns t dh data hold time 10 ns t dl data latch time 50 ns t init (1) write inhibit period after power-up 5 20 ms t db time to device busy 80 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) a write pulse of less than 20ns duration will not initiate a write cycle.
cat28c17a 6 doc. no. 1075, rev. b address ce oe we t rc data out da ta v alid da ta v alid t ce t oe t oh t aa t ohz t hz v ih high-z t lz t olz device operation read data stored in the cat28c17a is transferred to the data bus when we is held high, and both oe and ce are held low. the data bus is set to a high impedance state when either ce or oe goes high. this 2-line control architec- ture can be used to eliminate bus contention in a system environment. figure 4. byte write cycle [we controlled] address ce oe we t as data in da ta v alid t cs t ah t ch t wc t oeh t dl t dh t ds t oes t wp rdy/busy t db data out high-z ready/busy (rdy/busy) the rdy/busy pin is an open drain output which indicates device status during programming. it is pulled low during the write cycle and released at the end of programming. several devices may be or-tied to the same rdy/busy line. figure 3. read cycle
cat28c17a 7 doc. no. 1075, rev. b address ce we oe i/o 7 d in = x d out = x d out = x t oe t oeh t wc t oes byte write a write cycle is executed when both ce and we are low, and oe is high. write cycles can be initiated using either we or ce, with the address input being latched on the falling edge of we or ce, whichever occurs last. data, conversely, is latched on the rising edge of we or ce, whichever occurs first. once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. figure 5. byte write cycle [ce controlled] address ce oe we rdy/busy t as data in da ta v alid t ah t wc t oeh t dh t ds t oes t dl t ch t cs t cw t db data out high-z figure 6. data polling data polling data polling is provided to indicate the completion of a byte write cycle. once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on i/o 7 (i/o 0 ?i/o 6 are indeter- minate) until the programming cycle is complete. upon completion of the self-timed byte write cycle, all i/o?s will output true data during a read cycle.
cat28c17a 8 doc. no. 1075, rev. b hardware data protection the following is a list of hardware data protection fea- tures that are incorporated into the cat28c17a. (1) v cc sense provides for write protection when v cc falls below 3.0v min. (2) a power on delay mechanism, t init (see ac charac- teristics), provides a 5 to 20 ms delay before a write sequence, after v cc has reached 3.0v min. (3) write inhibit is activated by holding any one of oe low, ce high or we high. (4) noise pulses of less than 20 ns on the we or ce inputs will not result in a write cycle.
cat28c17a 9 doc. no. 1075, rev. b ordering information notes: (1) the device used in the above example is a cat28c17ani-20t (plcc, industrial temperature, 200 ns access time, tape & reel). prefix device # suffix 28c17a n i t product number t ape & reel package p: pdip n: plcc j: soic (jedec) k: soic (eiaj) -20 cat optional company id t emperature range blank = commercial (0 ? c to +70 ? c) i = industrial (-40 ? c to +85 ? c) a = automotive (-40 ? to +105 ? c)* speed 20: 200ns * -40 ? c to +125 ? c is available upon request l: pdip (lead free, halogen free) g: plcc (lead free, halogen free) w: soic (jedec) (lead free, halogen free) x: soic (eiaj) (lead free, halogen free)
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: 1075 revison: b issue date: 04/19/04 copyrights, trademarks and patents t rademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history e t a dn o i s i v e rs t n e m m o c 4 0 0 2 / 9 2 / 3a s a e r a l l a n i s e g a k c a p n e e r g d e d d a 4 0 / 9 1 / 4 0b n o i t a n g i s e d t e e h s a t a d e t e l e d m a r g a i d k c o l b e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u y r o t s i h n o i s i v e r e t a d p u r e b m u n v e r e t a d p u
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